Difference between revisions of "Scriber-Breaker"

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== Resources ==
== Resources ==
===== SOPs & Troubleshooting =====
===== SOPs & Troubleshooting =====
* [https://caltech.box.com/s/f02g7mjwi4asprd2ekiiotq6c09gp2bc Dynatex GST-150 Operation SOP and Troubleshooting Guide]
* [https://caltech.box.com/s/f02g7mjwi4asprd2ekiiotq6c09gp2bc Dynatex GST-150 Operation SOP and Troubleshooting Guide]
* [https://caltech.box.com/s/6sv7l95xxx8927f19sv04vcycx2p8yhq Dynatex GST-150 Operation Quick Reference Guide]
 
===== Labrunr Reservation Rules:=====
===== Labrunr Reservation Rules:=====
{| class="wikitable"
{| class="wikitable"

Latest revision as of 14:58, 29 July 2022

Scriber-Breaker
Dynatex-GST-150 Scriber-Breaker.jpg
Instrument Type Support Tools,
Substrate Processing
Techniques Wafer & Chip Scribing,
Scribe Breaking
Staff Manager Bert Mendoza
Staff Email bertm@caltech.edu
Staff Phone 626-395-4075
Reserve time on LabRunr
Request training by email
Sign up for Scriber email list
Lab Location B213 Steele
Lab Phone 626-395-1537
Manufacturer Dynatex
Model GST-150

Description

The scriber-breaker uses a dry scribing and breaking technique to allow cleaner separation of dies on a wafer than can be done with a wet cutting saw. Some advantages are that the elimination of deionized water protects delicate structures on the wafer surface, decreasing street sizes of existing wafers, and allowing for the dicing of difficult-to-manage substrates. Many compound semiconductors can be challenging when dicing, and the dry scribe-break technology is successful for such materials.

Applications
  • Scribing and/or breaking wafers

Resources

SOPs & Troubleshooting
Labrunr Reservation Rules:
Advanced Res (days) Limit per Res (hrs) Limit per week (hrs)
Weekday 7 4 12
Weeknight 7 6 18
Weekend 14 6 18

For reservations that DO NOT follow the reservation policy, email the tool manager BEFORE scheduling. Your reservation can be cancelled at any time by the tool manager if it does not follow the tool reservation policy.

Manufacturer Manuals

Specifications

Specifications
  • Accommodated Sizes: up to 6" wafers
  • Acceptable Materials: InP, GaAs, or Silicon substrates.